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ASIC and FPGA Top Level Verification to Ericsson

  • Req ID : 0

Required Skills

  • Synthesis
  • FPGA LAB
  • HW debugging
  • VHDL
  • ASIC Verification
  • Architecture
  • Test Scenario Development
  • Verilog
  • C Programming

Description

You will be part of the Digital ASIC and FPGA Top Level Verification team with responsibilities for Emulation in projects, from specification of test

scenarios to verified design.

 

• Collect requirements and participate in review of specifications

• Responsible for driving the Emulation activities including synthesis, compilation and debug for the emulator

• Analyze the architecture and define/improve test scenarios

• Developer test cases and low level driver for testbenches

• Execute test cases on ASIC, FPGA, and system level

• Work with ASIC and FPGA post silicon verification

• Apply continuous improvements of products and processes

 

• Experience on Palladium, Zebu or Veloce synthesis, compilation and debug

• Experience in C programming

• Experience in VHDL and Verilog language

• Experience from HW debugger usage in lab, (e.g. Lauterbach, Green Hill, JTAG)

• Good English proficiency in writing and speaking

• A Bachelor's or Master’s degree in Electrical Engineering (or equivalent)

• At least 7 years of relevant work experience

 

When applying for the assignment

self-assessment on all skills mentioned below (none - novice - intermediate - senior - expert)

Full namn of consultant/DoB/occupation today/ nationality/onsite after pandemic. add as appendix.

 

Required skills

ASIC Know how

FPGA know how

ASIC and FPGA post silicon verification

Emulation activities

C programming

VHDL/Verilog language

HW debug in Lab