Latest contracts

ASIC Verification Engineer to Ericsson

  • Req ID : 0

Required Skills

  • ASIC
  • System Verilog
  • UVM

Description

Our Exciting Opportunity

We are now looking to strengthen our Design team with an ASIC Verification Engineer. Your role will include many different tasks, but focus will be on Digital Verification of blocks and sub-systems.

Our focus is on Lean and Agile ways of working. We coordinate in multi-functional development teams in which continuous improvement, innovation and knowledge sharing is part of the daily work.

If you want to hear more about this opportunity, and have the right background, we encourage you to apply!

 

You will

• Take full responsibility for verification of a design, being block or sub-system

• Define and implement UVM based test environments

• Break-down Requirements and create Verification Specifications and defining test cases

• Develop, run and debug test cases

• Continuously improve and optimize ways of working

• Generate documentation

• Secure design quality

• Develop competence in technical domain

 

To be successful in the role you must have

• A MSc degree in a technical field or the equivalent level of education

• Several years’ experience from verification using System Verilog and UVM.

• Experience in developing verification test plans and directed/randomized test cases

• Good communication in English

• Skills in result-driven and meet expectations

 

Additional Requirements

• Experience from Formal Verification

Experience in Agile way of working

 

Please fill in a self assessment for the profile according to the below mandatory/meritorious skills (none-novice-intermediate-senior-expert)

ASIC know-how

Formal verification

VHDL/Verilog system

Develop, Run & Debugg Test cases

UVM

 

 

Full namn of consultant/DoB/occupation today/ nationality/onsite after pandemic. add as appendix.